A low-dropout or LDO regulator is a DC linear voltage regulator, which can operate with a very small input-output differential voltage. The advantages of a low dropout voltage regulator include a lower minimum operating voltage, higher efficiency operation and lower heat dissipation. The main components of a LDO regulator are an output power transistor (e.g. FET or bipolar transistor) and a differential amplifier (error amplifier). One input of the differential amplifier monitors the fraction of the output determined by a feedback voltage divider having a given divider ratio. The second input to the differential amplifier is from a stable voltage reference (e.g. bandgap reference). If the output voltage rises too high relative to the reference voltage, the drive to the output power transistor changes to maintain a constant output voltage.
Usual LDO applications require source capability by using one output transistor (output device) only, and usual LDO implementations therefore have a sourcing output transistor stage only. Any topology with sink-and-source capability will require a second output transistor and hence more silicon area and corresponding control circuitry which will increase also the quiescent current consumption. The sink capability of a LDO regulator with source transistor output stage is limited by its internal circuit current consumption. Especially for very low-power LDO regulators or for the low-power mode of LDO regulators, the current consumption of the internal circuitry is in the range of a few μA (Milliampere) or even far below 1 μA. Therefore there is nearly no sink capability available for low-power LDO regulators with only source transistor output stage.
If the LDO regulator is operated at higher temperature, e.g. above 85 degrees Celsius or even up to 125 degrees Celsius, the leakage current of a big output transistor starts to get relevant and could exceed the sink capability. The result would be an increase of LDO output voltage, which could in the worst case jump up to the LDO input voltage so that the regulation capability of the LDO regulator would be completely lost.
In order to overcome this problem, a voltage monitor and clamping circuitry could be used. The drawback of this solution is additional current consumption by such circuitry, which may not be acceptable for ultra-low-power designs. Another solution could be a LDO regulator with source-sink output stage as mentioned above. Again, such output stage requires more complex control and requires maintaining the loop stability for the whole circuitry, and furthermore will cause additional current consumption.
Another solution could be to add a constant-current sink with a fixed value of the maximum expected leakage current of the source output transistor. However, this approach would again increase the current consumption, even at room temperature.
It is a challenge for engineers designing LDO regulators to efficiently compensate leakage current, i.e. without additional power consumption and without complex control.
Known attempts of addressing this issue fail to match the output device leakage current over the full relevant temperature range. Specifically, the matched leakage current and the actual leakage current will differ significantly from each other either at higher temperature, or, if designed to match at higher temperature, the matched leakage current will require too high a value at the lower temperature range, thereby increasing the quiescent current of the LDO circuitry.